The high performance dual channel navigation receiver MSR1842 is a dual channel radio frequency baseband integrated receiver. The two RF channel uses an orthogonal down conversion scheme. It can be completely configured, the single channel RF local oscillator is adjustable, the RF input bandpass filter is optional and the bandwidth is adjustable, and the bandwidth of the analog IF output low pass / bandpass filter is adjustable. A radio frequency channel can be configured with a flexible dual channel radio frequency baseband integrated receiver. The RF channel can be configured as GPS L1, GPS L2, GPS L5C, GLONASS L1, the dipper generation, the two generation of Beidou B1 frequency points, the Beidou two generation B2 frequency points, the two Bei Dou B3 frequency points, 2.4G and other receivers.

Main uses:

Development of a dual channel satellite navigation receiver

Attitude measurement of two channel moving carrier for navigation receiver

Research and design of dual channel anti-jamming navigation receiver algorithm

Research and design of multipath measurement and algorithm for dual channel receiver

Research and design of high dynamic satellite navigation receiver algorithm

Research and design of high sensitivity satellite navigation receiver algorithm

Research and design of high precision satellite navigation receiver algorithm

Algorithm research and design development of multimode satellite navigation receiver

Hardware resource configuration:

Adopt the high-speed floating point processor TMS320C6713B of TI company, the main frequency 300MHz, reaches 2400MIPS, has the strong universal signal processing ability;

The ALTERA StratixII EP2S90F1020I4 chip has abundant gate resources, which can meet the vast majority of signal processing hardware programming and control capabilities.

The dual channel orthogonal frequency mixer is an independent RF channel. Each channel is composed of an independent two stage front end LNA, a RF SAW, a local oscillator frequency synthesizer, a quadrature mixer, a mid frequency low pass / band pass filter.

Four independent AD sampling channels. The AD chip is composed of AD9233-125 of Analog company, 12 bits quantization bits, and the highest 125M sampling rate.

Reference clock crystal oscillator on board: 10MHz, 1PPM, 0.5Vpp temperature supplement crystal oscillator (can be used for reference clock input, on board clock can also be used as reference for other circuits).

1 x 16Mb 16 bit bus FLASH chip, which is used to store DSP running code and a large number of user nonvolatile data.

1 x x 128Mb 32 bit bus SDRAM, expand DSP external memory resources;

1 x x 64KB EEPROM, which is used to store user nonvolatile data.

1 x x 4Mb 16 bit bus SRAM, expand FPGA external memory resources;

1 high precision real time clock module (RTC), which saves real-time time information and does not lose power.

8 user indicator lights;

1 system reset buttons;

1 configuration switch;

Interface type:

1 FPGA AS interfaces;

1 FPGA JTAG interfaces;

1 DSP JTAG interfaces;

2 RF input interface, MCX joint;

10MHz clock output on the 1 road board, MCX joint;

1 external 10MHz reference clock input, MCX joint

2 RS232 serial port;

2 RS422 differential serial port;

The 1 way USB2.0 interface, the interface chip is Cypress’s CY7C68013, supports 480Mbits high-speed transmission;

1 50pin FPGA IO expansion interface to facilitate user interface expansion;

3 high-speed FPGA IO expansion ports, SMA interface input / output;